1. Field of the Invention
The invention generally relates to memory access.
2. Description of the Related Art
FIG. 1 illustrates a prior art memory system 100 comprising a memory controller 110 and a memory 120. Memory controller 110 is coupled to memory 120 by a set of address lines 112, a set of address/data lines 114, control lines 116, and a clock (CLK) line 118 to clock memory 120 for synchronous memory access.
With reference to a read access timing diagram 200 of FIG. 2, memory controller 110 requests a read access to memory 120 by outputting a high-order address portion (A1H) over address lines 112, a low-order address portion (A1L) over address/data lines 114, and a read command, an active address valid (/ADV) control signal, and an active chip enable (CE) control signal over control lines 116. Memory 120 latches address portions A1H and A1L in response to the active /ADV signal, accesses stored data words (D1, D2, D3, and D4) starting at the address A1 formed by concatenating address portions A1H and A1L, and outputs data words D1, D2, D3, and D4 to memory controller 110 over address/data lines 114 in successive clock cycles.
Where memory 120 has an access latency of two clock cycles and where address/data lines 114 carry a 16-bit data word at a time, a single read access of 64 bits of data (four 16-bit data words) at address A1 is performed in six clock cycles. After completion of this read access and a precharge operation for memory 120, another access may be initiated to read another 64 bits of data at an address A2. As illustrated in FIG. 2, this second read access may be initiated eight clock cycles after the first read access is initiated. Four successive accesses to read 256 bits of data (16 16-bit data words) may therefore be performed in 30 clock cycles, that is 3×8 clock cycles for the first three accesses plus 6 clock cycles for the fourth access.
In some cases, the latency penalty incurred when accessing data at different memory locations (e.g., A1 and A2 above), because separate memory access operations are conventionally required, may be too great. Accordingly, what is needed are methods and apparatus for reducing access times to data at different memory locations.